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Wireless Components
PLL-Frequency Synthesizer PMB 2304R Version 2.1
Specification June 2002
preliminary
Revision History: Current Version: 06.02 Previous Version:Data Sheet Page (in previous Version) Page (in current Version) Subjects (major changes since last revision)
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1.
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PMB 2304R
preliminary
Productinfo
Productinfo
General Description The PMB 2304R PLL is a high speed Package: CMOS IC, especially designed for use in battery powered radio equipment and mobile telephones and serves as a functional replacement of the PMB 2307R. The primary applications are in digital cellular and cordless systems e.g. GSM 900/1800/1900 and DECT systems. The wide range of dividing ratios also allows application in analog systems. Low operating current consumption (typically 3.5 mA) High input sensitivity, high input frequencies (220 MHz) Large dividing ratios for small channel spacing A counter 0 to 127 N counter 3 to 16.383 R counter 3 to 65.535 Serial control (3-wire bus: data, clock, enable) for fast programming (fmax ~ 10 MHz) Switchable polarity and phase detector current programmable 2 Multifunction outputs frn, fvn outputs of the R- and N/A- counters for test Output port (e.g. for standby of the prescaler) External current setting for PD output Lock detect output with quasidigital lock detect
Switchable modulus trigger edge Serial control (3-wire bus: data, clock, enable) for fast programming (fmax ~ 10 MHz)
DECT
Ordering Information
Type PMB 2304R Ordering Code Q67106-H9100 Package P-TSSOP-16
Wireless Components
Product Info

Application
GSM 900 / 1800 / 1900
Fast modulus switchover for 65-MHz operation
Synchronous programming of the counters (N-, N/A-, R-counters) and system parameters
Linearization of the phase detector output by current sources
Extremely fast phase detector without dead zone

Features
Analog systems
Specification, June 2002
1
Table of Contents
1 2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.3 3.4 3.5 3.6 4 4.1 4.2 4.3 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.2 5.3 5.4 5.5 5.6 5.7 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Data acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Application Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Typical Supply Current IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Phase detector outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Serial Control Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Programming Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Pulse Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Serial Control Data Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Diagram Input Sensitivity FI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
2
Product Description
Contents of this Chapter
2.1 2.2 2.3 2.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
PMB 2304R
preliminary
Product Description
2.1 Overview
The PMB 2304R PLL is a high speed CMOS IC, especially designed for use in battery powered radio equipment and mobile telephones and serves as a functional replacement of the PMB 2307R. The primary applications are in digital cellular and cordless systems e.g. GSM 900/1800/1900 and DECT systems. The wide range of dividing ratios also allows application in analog systems.
2.2 Features
Low operating current consumption (typically 3.5 mA) High input sensitivity, high input frequencies (220 MHz) Extremely fast phase detector without dead zone Linearization of the phase detector output by current sources Synchronous programming of the counters (N-, N/A-, R-counters) and system parameters Fast modulus switchover for 65-MHz operation Switchable modulus trigger edge Serial control (3-wire bus: data, clock, enable) for fast programming (fmax ~ 10 MHz) Large dividing ratios for small channel spacing A counter 0 to 127 N counter 3 to 16.383 R counter 3 to 65.535 Serial control (3-wire bus: data, clock, enable) for fast programming (fmax ~ 10 MHz) Switchable polarity and phase detector current programmable 2 Multifunction outputs frn, fvn outputs of the R- and N/A- counters for test Output port (e.g. for standby of the prescaler) External current setting for PD output Lock detect output with quasidigital lock detect
Wireless Components

2-2
Specification, June 2002
PMB 2304R
preliminary
Product Description
2.3 Application
GSM 900 / 1800 / 1900 DECT Analog systems
2.4 Package Outlines
Wireless Components

P-TSSOP-16
2-3
Specification, June 2002
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.5 3.6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Data acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
PMB 2304R
preliminary
Functional Description
3.1 Pin Configuration
RI VSS EN DA CLK VDD MOD NC
1 2 3 4 5 6 7 8
16 15 14
LD M FO2 M FO1 VDD1 PD VSS1 FI NC
PM B 2304R
13 12 11 10 9
Pin_config.wmf
Figure 3-1
Pin Configuration
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function Pin No. 1 Symbol RI
STD BY 5 00K
Equivalent I/O-Schematic
Function Reference Frequency Input with highly sensitive preamplifier for 16-bit R-counter. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals.
P in1 RI 2 pF ESD
5 60
STDBY
2
VSS
Ground for serial control logic.
Wireless Components
3-2
Specification, June 2002
PMB 2304R
preliminary
Functional Description
3
EN
P in 3
560 *2pF
EN
3-Line Bus: Enable Enable line of the serial control with internal pull-up resistor. When EN = H the input signals CLK and DA are disabled internally. When EN = L the serial control is activated. The received data are transferred into the latches with the positive edge of the EN-signal.
ESD
4
DA
75k
P in 4
560 *2pF
DA
3-Line Bus: Data Serial data input with internal pull-up resistor. The last two bits before the ENsignal define the destination address. In a byte-oriented data structure the transmitted data have to end with the EN-signal, i.e. bits to be filled in (don't care) are transmitted first.
ESD
5
CLK
75k
P in 5
560 *2pF
CLK
ESD
75k
3-Line Bus: Clock Clock line with internal pull-up resistor. The serial data are read into the internal shift register with the positive edge (see pulse diagram for serial data control).
6 7
VDD
Positive supply voltage for serial control logic. Modulus Control Output for external dual modulus prescaler. The modulus output is low at the beginning of the cycle. When the A-counter has reached its set value, MOD switches to high. When the N-counter has reached its set value, MOD switches to low again, and the cycle starts from the top. When the prescaler has the counter factor P or P + 1 (P for MOD = H, P + 1 for MOD = L), the overall divider factor is NP + A. The value of the A-counter must be smaller than that of the N-counter. The trigger edge of the modulus signal to the input signal can be selected (see programming tables and MODA, B) according to the needs of the prescaler. In single modulus operation and for standby operation in dual modulus operation, the output is low.
MOD
p in 7 2pF
MOD
ES D
Wireless Components
3-3
Specification, June 2002
PMB 2304R
preliminary
Functional Description
8 9 10
NC NC FI
STD BY 5 00K
not connected not connected VCO-Frequency Input with highly sensitive preamplifier for 14-bit N-counter and 7-bit A-counter. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals.
P in10 FI 2 pF ESD
5 60
STDBY
11
VSS1
Ground for the preamplifiers, counters, phase detector and charge pump. (Note: The pins VDD and VDD1 respectively VSS and VSS1 have to have the same supply voltage.)
12
PD
p in 1 2 *2 p F
PD
ES D * O n ly th is p in h a s lim ite d b u ild -in E S D p ro te ctio n
Phase Detector Tristate charge pump output. The integrated, positive and negative current sources can be programmed with respect to their current density by means of the serial control. Activation and deactivation depend on the phase relationship of the scaled-down input signals FI:N, RI:R. (See phase detector output waveforms.) frequencyfV < fR or fV lagging:p-channel current source active frequencyfV > fR or fR leading:n-channel current source active frequencyfV = fR and PLL locked:current sources are switched off, PD-output is tristate In standby mode the PD-output is set to tristate. The assignment of the current sources to the output signals of the phase detector can be swapped in it's polarity, i.e. the sign of the phase detector constant can be controlled. Positive supply voltage for the preamplifiers, counters, phase detector and charge pump.
13
VDD1
Wireless Components
3-4
Specification, June 2002
PMB 2304R
preliminary
Functional Description
14
MFO1
p in 1 4 2pF
M FO1
ES D
Multifunction Output for the signals fRN , V,, VN , and port1. -The signal fRN is the divided signal of the reference frequency. The L-time corresponds to 1/fRI respectively -In the port function the port 1 output signal is assigned to the information of the programmed status. The output switches with the rising edge of the EN-signal The standby mode does not affect the port function. Multifunction I/O-Pin for the external reference current setting IREF and the signals RN and fVN ( in testmode). -The signal fVN is the divided signal of FIinput. The L-time corresponds to 1/fFI respectively. Output levels are not specified, the signal should only be used for test purpose. -In the internal charge pump mode the reference current IREF at MFO2 determines the value of the PD-output current. Lock Detector Output (open drain). Unipolar output of the phase detector in the form of a pulse-width modulated signal. The LD-pulse width corresponds to the phase difference. In the locked state the LD-signal is at H-level. For standby mode see Standby Table. Only for ABL status 11 no gating of ABL impulse is performed.
15
MFO2
5 60 IR E F
M F 02 V REF Inte rn al C h arge P um p M od e & sta ndb y 2pF P in15
V REF
ESD
16
LD
p in 1 6 2pF
LD
ES D
Wireless Components
3-5
Specification, June 2002
PMB 2304R
preliminary
Functional Description
3.3 Functional Block Diagram
RI
1 6-B it R -C o u n te r
P h a se D e te cto r
D a ta R e g iste r and S ha d o w R e g iste r PD
IR E F M FO2
M o d u lu s C o n tro l
FI
1 4 -B it N -C o u n te r
7 -B it A -C o u n te r
D a ta R e g iste r
D a ta R e g iste r
S ha d o w R e g iste r
S h a d o w R e g iste r
S h ift R e g iste r
S h ift R e g iste r
CLK DA EN
S e ria l C o n tro l L o g ic
Figure 3-2
Functional Block Diagram
Wireless Components
3-6
S h ift R e g iste r
V
C h a rg e Pum p
R
R
L o ckD e te cto r
LD
V
M FO1
MOD
V DD1 V SS1
V DD V SS
Funct_block.wmf
Specification, June 2002
PMB 2304R
preliminary
Functional Description
3.4 General Description
The circuit consists of a reference-, A- and N-counter, a dual modulus control logic, a phase detector with charge pump output and a serial control logic. The setting of the operating mode and the selection of the counter ratios is done serially at the ports CLK, DA and EN. The operating modes allow the selection of single or dual operation, asynchronous or synchronous data acquisition, 4 different antibacklash-impulse times, 8 different PD-output current modes, polarity setting of the PD-output signal, adjustment of the trigger-edge of the MOD-output signal, 2 standby modes and the control of the multifunction outputs MFO1 and MFO2. The reference frequency is applied at the RI-input and divided by the R-counter. It's maximum value is 100 MHz. The VCO-frequency is applied at the FI-input and divided by the N- or N/A-counter according to single or dual mode operation. The maximum value at FI is 220 MHz at single-, and 65 MHz at dual mode operation. The phase and frequency sensitive phase detector produces an output signal with adjustable anti-backlash impulses in order to prevent a dead zone for very small phase deviations. Phase differences of less than 100 ps can be resolved. In general the shortest anti-backlash pulse gives the best system performance.
3.5 Programming
Programming of the IC is done by a serial data control. The contents of the message are assigned to the functional units according to the address. Single or dual mode operation as well as asynchronous or synchronous data acquisition is set by status 2 and should therefore precede the programming of the counters.
3.6 Data acquisition
The PMB 2304R offers the possibility of synchronous data acquisition to avoid error signals at the phase detector due to non-corresponding dividing factors in the counters produced by asynchronous loading. Synchronous programming guarantees control during changes of frequency or channel. That means that the state of the phase detector or the phase difference is kept maintained, and in case of "lock in", the control process starts with the phase difference "zero".
Wireless Components
3-7
Specification, June 2002
PMB 2304R
preliminary
Functional Description
This is done as follows: 1. Setting of synchronous data acquisition by status 2. 2. Programming of the R-counter, status 1 (optional)-data is being loaded into shadow registers. 3. Programming of the N- or N/A-counter-data is being loaded into shadow registers, the EN-signal starts the synchronous loading procedure. 4. Synchronous programming - which means data transfer of all data from the shadow registers to the data registers - takes place at that point in time when the respective counter reaches "zero + 1", the maximum repetition rate for channel change is therefore fFI:N. 5. Transfer of status 1 information into the corresponding data register is tied to the N-counter loading, but follows the loading of the N-data register in the distance of one N-counter dividing ratio, this guarantees that for example a new PD-current value becomes valid at the same time when the counters are loaded with the new data.
Synchronous avoids additional phase error caused by programming. Synchronous data acquisition is of especial advantage, when large steps in frequency are to be made in a short time. For this purpose a high reference frequency can be programmed in order to achieve rapid - "rough" - transient response. This method increases the fundamental frequency nearly by the square route of the reference frequency relation. When rough lock is achieved, another synchronous data transfer is needed to switch back to the original channel spacing. A "fine" lock in will finish the total step response. It may not be necessary to change reference frequency, but it make sense to perform synchronous data acquisition in any case. Especially for GSM, PCN, PCS, DECT, DAMPS, PHP systems the synchronous mode should be used to get best performance of the PMB 2304R.
Standby Condition: The PMB 2304R has two standby modes (standby 1, 2) to reduce the current consumption. Standby 1 switches off the whole circuit, the current consumption is reduced below 1 A. Standby 2 switches off the counters, the charge pump and the outputs, only the preamplifiers stay active. For the influence on the output signals see standby table (5-10).
fRN, fVN, RN, VN are the inverted signals of fR, fV,R, V.
Wireless Components
3-8
Specification, June 2002
4
Applications
Contents of this Chapter 4.1 4.2 4.3 PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Application Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
PMB 2304R
preliminary
Applications
4.1 PCB Layout
oben.wmf
Figure 4-1
Top Side
unten.wmf
Figure 4-2
Bottom Side
Wireless Components
4-2
Specification, July 1999
PMB 2304R
preliminary
Applications
4.2 Application Board
stromlauf.wmf
Figure 4-3
Application board
Wireless Components
4-3
Specification, July 1999
PMB 2304R
preliminary
Applications
4.3 Bill of material
Table 4-1 Nr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Reference C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 IC1 IC2 J1 J2 J3 N2 R1 R2 Symbol name CAP CAPELK CAP CAP CAP CAP Technology 10p 47 10p 10p 10p
220pF 330pF 30pF 100p 100n 100p 100n 47 5.6nF 150p 10nF 1nF 47 PMB2314T PMB2304R 5 Pin JUMPER_2SMD06031 JUMPER_2SMD06031 1500MHz 10k 10k 10k 4k7 4k7 4k7 27k 124k
CAP CAP CAP CAP CAP CAP CAPELK CAP CAP CAP CAP CAPELK PMB2314T PMB2305 CON-5 JUMP-2SMD0603 JUMP-2SMD0603 VCO2 RES RES RES RES RES RES RES RES
R3 R4 R5 R6 R7 R8
Wireless Components
4-4
Specification, July 1999
PMB 2304R
preliminary
Applications
33 34 35 36 37 38 39 40 41 42 43 44 45
R9 R10 R11 R12 R13 R14 R15 R16 R17
-
RES RES RES RES RES RES RES RES RES SMA SMA SMA SMA
8.2k 18 56 18 18 47 10 10 22k SMA_stehend SMA_stehend SMA_stehend SMA_stehend
X1 X2
Wireless Components
4-5
Specification, July 1999
5
Reference
Contents of this Chapter 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Phase detector outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Serial Control Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Programming Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Pulse Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Serial Control Data Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Diagram Input Sensitivity FI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
PMB 2304R
preliminary
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Range
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Range Parameter Symbol Limit Values min max Unit Remarks
Supply Voltage Input Voltage Output Voltage Power dissipation per output Total power dissipation Ambient temperature Storage temperature Thermal Resistance ESD Integrity except @Pin 12 (PD) (according to MIL833 Method 3015.7) ESD Integrity except @Pin 12 (PD) (according to MIL833 Method 3015.7)
VDD V1 VQ PQ Ptot TA Tstg RthJA VESD
-0.3 -0.3 GND
6 VDD + 0.3 VDD 10 300
V V V mW mW C C K/W KV in operation
-40 -50
85 125 180 1
VESD
400
V
Wireless Components
5-2
Specification, June 2002
PMB 2304R
preliminary
Reference
5.1.2
Operating Ratings
Within the operating ratings the IC operates as described in the circuit description. The AC/DC characteristic limits are not guaranteed.
Table 5-2 Operating Ratings, Supply Voltage VVCC= 2.7 V .. 4.5 V, Ambient temp. TAMB= -30C ... + 85C Parameter Symbol Limit Values min Supply Voltage Input frequency dual Input frequency single HF-mode Input frequency single LF-mode Input reference frequency Input frequency dual mode Input frequency single HF-mode Input frequency single LF-mode Input reference frequency PD-output current PD-output voltage PD-output voltage Ambient temperature VDD FI FI FI RI FI FI FI RI / IPD VPD
VPD
Unit
Test Conditions
L
Item
max 5.5 65 220 90 100 V MHz MHz MHz MHz MHz MHz MHz MHz mA V c C VDD = 4.5- 5.5V VDD = 2.7V VDD = 4.5...5.5V VDD = 4.5...5.5V VDD = 4.5...5.5V VDD = 4.5...5.5V VDD = 2.7V VDD = 2.7V VDD = 2.7V VDD = 2.7V
2.7 0.1 0.1 0.1
0.1 0.1 0.1
30 90 35 20 4
0.5 0.5 -40
VDD - 0.5 VDD - 0.5 85
TA
5.1.3
Typical Supply Current IDD
All pins are protected against ESD. Unused inputs without pullup resistors must be connected to either VDD or VSS.
Table 5-3 Typical Supply Current IDD Parameter Symbol min Supply voltage Supply current: single mode HF dual mode standby 2 standby 1 IDD IDD IDD IDD 1.63 1.76 0.11 2.6 2.80 0.62 2.94 3.17 0.75 1 mA mA mA A VDD 2.7 5 Limit Values max 5.5 V FI = 50MHz VFI = 150mVrms RI = 10MHz VRI = 150mVrms IPD = 0.25mA Iref = 100 A Unit Test Conditions L Item
Wireless Components
5-3
Specification, June 2002
PMB 2304R
preliminary
Reference
5.1.4
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production.
Table 5-4 AC/DC Characteristics with Ambient temp. Tamb= -20 .. 85 C, Supply Voltage VVCC = 2.7 .. 4.5V Symbol min Limit Values typ max Unit Test Conditions L Item
Input Signals DA, CLK, EN (with internal pull-up resistors) H-input voltage L-input voltage Input capacity H-input current L-input current Input Signal RI Input voltage Input voltage Slew rate Input capacity H-input current L-input current Input Signal FI (dual mode) Input voltage Input voltage Slew rate Input capacity H-input current L-input current CI IH IL -30 VI VI 180 50 4 3 30
mVrms mVrms = 4...65MHz, VDD = 4.5V = 10...25MHz, VDD = 2.7V
3.1 3.2 3.3
VIH VIL CI IH IL
0.7- VDD
VDD
0.3- VDD
V V pF A A VI = VDD = 5.5V VI = GND
1.1 1.2
5 10 -60
1.3 1.4
VI VI
100 100 4
mVrms mVrms
= 4...100MHz, VDD = 4.5V = 4...30MHz, VDD = 2.7V
2.1 2.2 2.3
V/s
VDD = 2.7...5.5V
CI IH IL -30
3 30
pF A A VI = VDD = 5.5V VI = GND
2.4 2.5
V/s pF A A
VDD = 2.7...5.5V
VI = VDD = 5.5V VI = GND
3.4 3.5
Input Signal FI (single HF-mode) Input voltage Input voltage Input voltage Slew rate Input capacity H-input current L-input current CI IH IL -30 VI VI VI 200 200 50 4 3 30
mVrms mVrms mVrms = 4...200MHz, VDD = 4.5V = 4...90MHz, VDD = 2.7V = 10...40MHz, VDD = 4.5V
4.1 4.2 4.3 4.4
V/s
pF A A
VDD = 2.7...5.5V
VI = VDD = 5.5V VI = GND
4.5 4.6
Wireless Components
5-4
Specification, June 2002
PMB 2304R
preliminary
Reference
Table 5-4 AC/DC Characteristics with Ambient temp. Tamb= -20 .. 85 C, Supply Voltage VVCC = 2.7 .. 4.5V Symbol min Input Signal FI (single LF-mode) Input voltage Input voltage Slew rate Input capacity H-input current L-input current Output Current /IPD/ Current mode: "0.175 mA" "0.25 mA" "0.35 mA" "0.5 mA" "0.7 mA" "1.0 mA" "1.4 mA" "2.0 mA" Standby" Output Tolerance IPD IPD / IPROG IPD / IPROG -10% -5% 2.5% +0%
VPD = VDD/2, VDD = 2.7V VPD = 0.5...2.2V, VDD = 2.7V
7.1 7.2 6.1
Limit Values typ max
Unit
Test Conditions
L
Item
VI VI
100 100 4
mVrms mVrms
= 4...90MHz, VDD = 4.5V = 4...35MHz, VDD = 2.7V
5.1 5.2 5.3
V/s
VDD = 2.7...5.5V
CI IH IL -30
3 30
pF A A VI = VDD = 5.5V VI = GND
5.4 5.5
IPROG IPROG IPROG IPROG IPROG IPROG IPROG IPROG /IPD/
-20% -20% -20% -20% -20% -15% -15% -10%
0.175 0.25 0.35 0.5 0.7 1.0 1.0 2.0 0.1
+20% +20% +20% +20% +20% +15% +15% +10% 1
mA mA mA mA mA mA mA VDD = 4.5V mA VDD = 4.5...5.5V VPD = VDD/2 IREF = 100
6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10
Input Voltage MFO2 (Internal charge pump mode) Reference voltage
VREF
0.9
1.1
1.3
V
VDD = 2.7...5.5V IREF = 100A
Output Signal MFO1 (push pull) H-output voltage L-output voltage H-output voltage L-output voltage Rise time Fall time Rise time Fall time VQH VQL VQH VQL tR tF tR tF 2.5 2.0 5 4 VDD - 1 1 10 10 12 12 VDD - 1 1 V V V V ns ns ns ns
VDD = 4.5...5.5V,IQH= -2mA VDD = 4.5...5.5V,IQL= 2mA VDD = 2.7V,IQH=-1.2mA VDD = 2.7V,IQL=1.2mA
VDD = 4.5...5.5V,CI= 10pF 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8
VDD = 4.5...5.5V,CI= 10p
VDD = 2.7V,CI=10pF VDD = 2.7V,CI=10pF
Wireless Components
5-5
Specification, June 2002
nA
8.1
PMB 2304R
preliminary
Reference
Table 5-4 AC/DC Characteristics with Ambient temp. Tamb= -20 .. 85 C, Supply Voltage VVCC = 2.7 .. 4.5V Symbol min Output Signal MFO2 (push pull) H-output voltage L-output voltage H-output voltage L-output voltage Rise time Fall time Rise time Fall time VQH VQL VQH VQL tR tF tR tF 2 2 3 3 VDD - 1 1 10 10 10 10 VDD - 1 1 V V V V ns ns ns ns
VDD = 4.5...5.5V,IQH= 2mA VDD = 4.5...5.5V,IQL= 2mA VDD = 2.7V,IQH= 1.2mA VDD = 2.7V,IQL= 1.2mA
VDD = 4.5...5.5V,CI= 10pF 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8
Limit Values typ max
Unit
Test Conditions
L
Item
VDD = 4.5...5.5V,CI= 10p
VDD = 2.7V,CI=10pF VDD = 2.7V,CI=10pF
Output Signal LD (n-channel open drain) L-output voltage H-output current Fall time Fall time VQL IQH tF tF 3 5 0.4 5 10 12 V A ns ns
VDD = 2.7...5.5V, IQL = 0.3mA
11.1
VDD = 2.7...5.5V
VDD = 4.5...5.5V,CI=10pF
11.2 11.3 11.4
VDD = 2.7V,CI=10pF
Output Signal MOD (push pull) H-output voltage L-output voltage H-output voltage L-output voltage Rise time Fall time Propagation delay time H-L to FI Propagation delay time L-H to FI Rise time Fall time Propagation delay time H-L to FI Propagation delay time L-H to FI VQH VQL VQH VQL tR tF tDQHL tDQHL tR tF tDQHL tDQHL 1.5 1.3 8 8 3.2 2 15 15
VDD-0.4 VDD-0.4
V 0.4 V V 0.4 3 3 12 12 5 5 V ns ns ns ns ns ns ns ns
VDD = 4.5...5.5V, IQH = -0.5mA VDD = 4.5...5.5V IQL = 0.5mA VDD = 2.7V, IQH = - 0.3mA VDD = 2.7V, IQL= 0.3mA VDD = 4.5...5.5V, CI = 5pF VDD = 4.5...5.5V, CI = 5pF VDD = 4.5...5.5V, CI = 5pF
12.1
12.2
12.3 12.4 12.5 12.6 12.7
VDD = 4.5...5.5V, CI = 5pF
12.8
VDD = 2.7V, CI = 5pF VDD = 2.7V, CI = 5pF VDD = 2.7V, CI = 5pF VDD = 2.7V, CI = 5pF
12.9 12.10 12.11
12.12
This value is only guaranteed in lab.
Wireless Components
5-6
Specification, June 2002
PMB 2304R
preliminary
Reference
5.2 Phase detector outputs
RI
fR (RI:R) MOD A MOD B
FI
fV (FI:N) P-Channel PD Tri-State. Polarity pos. N-Channel
P-Channel PD Polarity Tri-State. neg. N-Channel LD
R
Polarity pos. (internal Signal)
V
Polarity pos. (internal Signal)
Frequency fV < fR or fV lagging
Frequency fV > fR or fV leading
Frequency fV = fR
Figure 5-1
Phase detector output signals
Wireless Components
5-7
Specification, June 2002
PMB 2304R
preliminary
Reference
5.3 Serial Control Data Format
Table 5-5 Serial Control Data Format (status 1,2) Status 1 Status 2 0 Data acquisition mode Mode 1 Mode 2 PD-polarity Standby 1 Standby 2 Anti-backlash pulse width 1 Anti-backlash pulse width 2 Preamplifier select Single / dual mode 1 2 3 4 5 6 EN 0 0 Port 1 PD-current 1 PD-current 2 PD-current 3 Address 0 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EN single low see table see table see table negative standby standby see table see table see table dual high asynchronous 1 synchronous
see table see table positive active active
Wireless Components
5-8
Specification, June 2002
PMB 2304R
preliminary
Reference
Table 5-6 Serial Control Data Format (N-, N/A-counter) Dual Mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 EN LSB 1 0 Address LSB 1 0 NCounter LSB MSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EN ACounter MSB Single Mode
Table 5-7 Serial Control Data Format (R-counter)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 EN
MSB
RCounter
LSB 1 1 Address
Wireless Components
5-9
Specification, June 2002
PMB 2304R
preliminary
Reference
5.4 Programming Tables
Table 5-8 Status Bits AntiBacklash Pulse Width 2 0 0 1 1 AntiBacklash Pulse Width 1 0 1 0 1 tW (typ.) [ns] 1.3 5 10 13* not recommended any application where continuous lock detect is required VDD = 5V
* No ABL gating performed
* In general the shortest anti-backlash pulse gives the best system performance
.
Table 5-9 Status Bits Single/Dual Mode 0 0 1 1 Preamplifier Select 0 1 0 1 FI-input frequency,single HF-mode FI-input frequency,single LF-mode FI-input frequency, dual-mode, FItrigger edge LH, MOD A FI-input frequency, dual-mode, FItrigger edge HL, MOD B Preamplifier Function Mode
Table 5-10 Standby Table Output Pins Status V Standby 1 Standby 2 low low MFO1 VN high high high high resistive resistive tristate tristate low low MFO2 LD PD MOD
Wireless Components
5 - 10
Specification, June 2002
PMB 2304R
preliminary
Reference
Table 5-11 Status Bits PD-Current 3 0 0 0 0 1 1 1 1 PD-Current 2 0 0 1 1 0 0 1 1 PD-Current 1 0 1 0 1 0 1 0 1 PD-Current Mode Ipd/mA 0.175 0.25 0.35 0.5 0.7 1 1.4 2
Table 5-12 Status Bits Mode 2 0 0 1 1 Mode 1 0 1 0 1 MFO 1 fRN V VN Port 1 Multifunction Output MFO 2 fVN RN RN Iref Remarks test mode external charge pump mode 1 external charge pump mode 2 internal charge pump mode
5.5 Pulse Diagram
FI
50%
50%
tDQLH
VQH VQL
tDQLH
tDQLH
tDQLH
MOD A
50%
50%
tR
VQH VQL
tF
MOD B
50%
50%
tR
tF
Figure 5-2
Pulse diagram
Wireless Components
5 - 11
Specification, June 2002
PMB 2304R
preliminary
Reference
5.6 Serial Control Data Input Timing
tWHCL VIH CLK VIL
tR
tF
tDS
VIH
DA
VIL
tCLE
tECL
VIH
EN
VIL
tWHEN VIH MFO1 MFO3 VIL
tDEP
Figure 5-3 Table 5-13 Parameter
Serial Control Data Input Timing
Symbol
Limit Values min max 12 40 20 20 20 40 10 1
Unit
Clock frequency H-pulsewidth (CL) Data setup Setup time-clock enable Setup time enable-clock H-pulsewidth (enable) Rise, fall time Propagation delay time EN-PORT
CL
MHz ns ns ns ns ns s s
tWHCL tDS tCLE tECL tWHEN tR, tF tDEP
Wireless Components
5 - 12
Specification, June 2002
PMB 2304R
preliminary
Reference
5.7 Diagram Input Sensitivity FI
Figure 5-4
Input sensitivity FI (single HF-mode)
Wireless Components
5 - 13
Specification, June 2002

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